LCDs are commonly used as display devices for compact electronic apparatuses, because they not only provide good quality images but are also very thin.
Referring to FIG. 3, a typical active matrix LCD 100 includes a first glass substrate 10, a second glass substrate 20 parallel to but spaced apart from the first substrate 10, a liquid crystal layer 30 sandwiched between the first and second substrates 10, 20, and a driving integrated circuit (IC) 120 bonded on the first substrate 10.
Referring also to FIG. 4, the first substrate 10 includes a number n (where n is a natural number) of gate lines 101 that are parallel to each other and that each extend along a first direction, and a number m (where m is also a natural number) of data lines 102 that are parallel to each other and that each extend along a second direction orthogonal to the first direction. The intersecting gate lines 101 and data lines 102 define a plurality of pixel units. The first substrate 10 also includes a plurality of thin film transistors (TFTs) 106 that function as switching elements. Each TFT 106 is provided in the vicinity of a respective point of intersection of the gate lines 101 and the data lines 102. The first substrate 10 further includes a plurality of pixel electrodes 103 formed on a surface thereof that faces toward the second substrate 20.
The second substrate 20 includes a plurality of common electrodes 105 opposite to the pixel electrodes 103. In particular, the common electrodes 105 are formed on a surface of the second substrate 20 that faces toward the first substrate 10. The common electrodes 105 are made from a transparent material such as ITO (indium-tin oxide) or the like.
FIG. 5 is an equivalent circuit diagram of one of the pixel units of the active matrix LCD 100. A gate electrode “g”, a source electrode “s”, and a drain electrode “d” of the TFT 106 are connected to a corresponding gate line 101, a corresponding data line 102, and a corresponding pixel electrode 103 respectively. Liquid crystal material of the liquid crystal layer 30 sandwiched between the pixel electrode 103 and a corresponding common electrode 105 on the second substrate 20 is represented as a liquid crystal capacitor Clc. Cgd is a parasitic capacitor formed between the gate electrode “g” and the drain electrode “d” of the TFT 106.
When the active matrix LCD 100 works, an electric field between the pixel electrode 103 and the common electrode 105 is generated. The electric field drives the liquid crystal material of the liquid crystal layer 30 at the pixel unit. Light beams from a light source such as a backlight pass through the first substrate 10, the liquid crystal layer 30, and the second substrate 20. The amount of light beams penetrating the first and second substrates 10, 20 is adjusted by controlling the strength of the electric field, in order to obtain a desired optical output for the pixel unit.
If an electric field with a certain direction is continuously provided to the liquid crystal material between the pixel electrode 103 and the common electrode 105, the liquid crystal material may deteriorate. Therefore in order to avoid this problem, pixel voltages that are provided to the pixel electrode 103 are switched from a positive value to a negative value with respect to a common voltage. This technique is referred to as an inversion drive method.
FIG. 6 is an abbreviated timing chart illustrating operation of the active matrix LCD 100. In the chart, the x-axis represents time, and the y-axis (not shown) represents voltage. Vg represents a plurality of scanning signals provided by the driving IC 120. Vd represents a plurality of gradation voltages provided by the driving IC 120. Vp represents a plurality of pixel voltages of the pixel electrode 103. ΔVg represents an impulse width of each of the scanning signals Vg, and equals the difference between a gate-on signal Von and a gate-off signal Voff. Vcom represents a common voltage of the common electrode 105 provided by an external circuit (not shown). ΔV represents a voltage distortion related to the pixel voltage Vd.
When a gate-on voltage Von is provided to the gate electrode “g” of the TFT 106 via the gate line 101, the TFT 106 connected to the gate line 101 turns on. At the same time, a gradation voltage Vd generated by the driving IC 120 is provided to the pixel electrode 103 via the data line 102 and the activated TFT 106 in series. The potentials of the common electrodes 105 are set at a uniform potential Vcom. Thus, an electric field is generated by the voltage difference between the pixel electrode 103 and the common electrode 105. The electric field is used to control the amount of light transmission of the corresponding pixel unit.
When a gate-off voltage Voff is provided to the gate electrode “g” of the TFT 106 via the gate line 101, the TFT 106 turns off. The gradation voltage Vd provided to the liquid crystal capacitor Clc while the TFT 106 was turned on should be maintained after the TFT 106 turns off. However, due to the parasitic capacitance Cgd between the gate electrode “g” and the drain electrode “d” of the TFT 106, the gradation voltage Vd provided to the pixel electrode 103 is distorted. This kind of voltage distortion ΔV is known as a kick-back voltage, and the kick-back voltage is obtained by following formula:
                    ΔV        =                                                                              C                  gd                                ·                Δ                            ⁢                                                          ⁢                              V                g                                                                    C                gd                            +                              Δ                ⁢                                                                  ⁢                                  V                  g                                                              =                                                    C                gd                            ·                              (                                                      V                    on                                    -                                      V                    off                                                  )                                                                    C                gd                            +                              Δ                ⁢                                                                  ⁢                                  V                  g                                                                                        (        1        )            
The voltage distortion ΔV always tends to reduce the pixel voltage Vp regardless of the polarity of the data voltage, as shown in FIG. 6.
In an ideal active matrix LCD 100, as shown by a dashed line Vd in FIG. 6, when the gate-on voltage Von is provided to turn on the TFT 106, the gradation voltage Vd is provided to the pixel electrode 103; and thereby, when the gate-off voltage Voff is provided to turn off the TFT 106, the provided gradation voltage Vd should be maintained as the pixel voltage. But in the actual active matrix LCD 100, as shown by a solid line Vp in FIG. 6, when the scanning signal Vg falls, the pixel voltage Vp is reduced by the kickback voltage ΔV.
An actual value of the voltage applied to the liquid crystal material is obtained from the area between the pixel voltage Vp line and the common voltage Vcom line in FIG. 6. In one time frame (“Frame”), the pixel voltage Vp is greater than the common voltage Vcom, and this area can be considered to be a ‘positive’ area. In an adjacent frame, the pixel voltage Vp is less than the common voltage Vcom, and this area can be considered to be a ‘negative’ area. When the active matrix LCD 100 is driven by an inversion drive method, the level of the common voltage Vcom must be adjusted to keep the positive area of the one frame equal to the negative area of the adjacent frame. Therefore, a common voltage Vcom satisfying the above-mentioned condition needs to be supplied to the common electrode 105 in order to suppress optical flicker phenomena of a display screen of the active matrix LCD 100.
Referring to FIG. 7, a typical burning system 510 for the active matrix LCD 100 is shown connected to the active matrix LCD 100. The burning system 510 is used to burn a parameter representing an optimum common voltage into an erasable programmable read only memory (EPROM) of the active matrix LCD 100 at the time the active matrix LCD 100 is manufactured. The EPROM thus stores the parameter for use when the active matrix LCD 100 is operated by an end user. The burning system 510 includes a first button 511 configured to adjust a common voltage provided to the active matrix LCD 100 by the burning system 510, and a second button 512 configured to launch a burning program of the burning system 510.
In operation of the burning system 510, the burning system 510 generates a plurality of common voltages, and provides the common voltages to drive the active matrix LCD 100. A human operator adjusts the common voltages until the optical flicker of the active matrix LCD 100 disappears. Then the second button 512 is pressed, and the burning program is launched to burn the parameter representing the current common voltage into the EPROM of the active matrix LCD 100.
The parameter burned into the active matrix LCD 100 is determined by the human operator observing the optical flicker of the active matrix LCD 100. This process involves manual work, and relies on the human operator's judgment. The process is somewhat inefficient, and may result in an inaccurate observation or an incorrect determination being made. Thus, the reliability of the burning system 510 may not be satisfactory.
What is needed, therefore, is a burning system for an LCD that can overcome the above-described deficiencies. What is also needed is a burning method using the burning system.